1. Field of the Invention
The invention relates to a method of manufacturing filled isolation trenches in silicon by applying Complementary Metal Oxide Semiconductor (CMOS) standard processes for forming dielectrically insulated regions (insulation trenches; isolation trenches) on a Silicon on Insulator (SOI) wafer. To this end, only silicon dioxide (SiO2) is to be used for the filling. The technique results in sealed cavities of voids within the trench. These remaining voids are advantageous with respect to a reduction of elastic stress. The technique leads to the filling of trenches having an aspect ratio ranging from small values to very high values with various angles of the sidewalls.
2. Description of Related Art
The conventional isolation trenches for the dielectric insulation of different circuit portions usually do not meet the requirements of micro electronic mechanic systems (MEMS) with respect to minimizing stress and using an equivalent fill material, which may, if required, be removed at defined positions in a later stage in a highly selective manner relative to silicon.
Most of the well-known techniques are based on the concept of avoiding voids. This is accomplished by either avoiding narrow portions or bottlenecks during the trench fill process (V-shaped trench profiles, specific deposition techniques) or by removing existing bottlenecks by a dedicated back etch process.
Avoiding voids may, for instance, be achieved by a V-shaped trench geometry including a specific edge design, cf. U.S. Pat. No. 6,180,490. Also in this case the aspect ratio of the trench to be filled is restricted.
In the known techniques for forming trench isolations of semiconductor devices in a semiconductor layer of an SOI wafer shallow trenches are used, which in most cases should be devoid of voids. U.S. Pat. No. 6,261,921 describes such a technique usable for shallow trenches, wherein a V-shaped trench is used and a silicon nitride layer is used for an additional edge retraction.
US-A 2002/0076915 describes a fill process with polysilicon deposited on an insulating layer. The method is used for SOI wafers for manufacturing integrated circuits, the method does, however, not allow high aspect ratios of the trench to be filled. As a special feature a tapering of the trench opening by back etching of overhanging material at the trench opening that builds up during the fill process is described in order to avoid voids.
A similar technique, however for trenches within the semiconductor (not an SOI wafer) with respect to shallow trenches having a depth of 1 μm or less is described in U.S. Pat. No. 6,140,207. Also in this case a tapering of the trench opening is realized by an oblique portion in the silicon.
U.S. Pat. No. 5,872,058 discloses a special deposition technique for a dielectric insulation layer (SiO2 or any other material). This technique uses special deposition conditions, wherein the deposition rate and the etch rate are adjusted with different gas concentrations such that any bottlenecks in trench are avoided during the fill process, thereby enabling a substantially void-free filling of trenches. The aspect ratio is stated to be 3:1 or higher. Also in this case a filling of A-shaped trench structures does not appear to be possible.